The continuing trend of scaling down integrated circuits has motivated the semiconductor industry to consider new techniques for fabricating precise components at sub-micron levels. One important area in semiconductor fabrication is forming the interconnecting structure within the integrated circuit and particularly connection between a transistor and other devices.
As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. In semiconductor devices it may be advantageous to build contact plugs for interlayer connections having high aspect ratio structures, as circuit density will be enhanced. In that light, the ability to precisely align contact plugs to their associated devices becomes a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
Forming contact plugs to regions in a semiconductor device are well known. See for example U.S. Pat. No. 6,518,626 describing a self-aligned contact to a source/drain region of a transistor. The contact is fabricated between transistor gate stacks having sidewall spacers, often formed of an oxide or nitride. The process includes forming an insulating layer, for example an oxide such as BPSG, over the gate stacks and etching through the insulating layer. The sidewall spacers on the gate stack protect the gate stack and allow for lateral margin during the etching process. The etching process, however, does remove some of the sidewall spacer. As the thickness of the spacer decreases with advances in semiconductor designs, removal of a portion of the spacer can create short circuits between the transistor gate stack and the conductive contact plug.
Removing doped oxide relative to un-doped oxide can be more difficult than removing an oxide relative to nitrite. Therefore, prior art used a nitride sidewall spacer and a layer of oxide over the gate stack. Prior self aligned contact processes used an etch process to remove the oxide (BPSG) selectively to nitride. Depending upon the selectivity used, a polymer layer is re-deposited on the sidewall spacer during the etch operation. The higher the selectivity the thicker the polymer layer becomes. As such, if too high of a selectivity is used the contact opening can become blocked with the polymer layer. Balancing the thickness of the polymer layer, etch selectivity, contact width and the thickness of the sidewall spacer is challenging. Prior etch processes have been limited to a selectivity of oxide to nitride in the range of less than 40:1.
Embodiments of the present invention describe methods to form self-aligned contact plugs that address the above challenges, the methods disclosed herein for use in the manufacture of semiconductor assemblies, which will become apparent to those skilled in the art from the following disclosure.